For the design of digital circuits (e.g., on the scale of very large scale integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as hardware description languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist, which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist, which is specific to a particular vendor's technology/architecture. During the mapping process small collections of logic operations and the signals between them are mapped into gates or LUTs in the case of FPGAs. Power can be minimized at this stage by maximizing the activity of the signals that are covered or mapped inside of the gates or LUTs, leaving lower activity signals to be routed on wires between the logic cells.
During placement of components on the chip, the algorithms used typically try to optimize the total wiring and the delay along critical paths by placing connected components and critical path cells close together. A reduction in power consumption can also be an objective during placement. In this case the objective is to make the wires for signals that are switching rapidly shorter.
Power becomes the bottleneck of next generation nano-scale IC (integrated circuit) designs due to the aggressive technology scaling. Circuit activity analysis is a key missing input for many kinds of power estimations and optimizations. In the current EDA (electronic design automation) industry, there is no low-cost solution for the activity analysis due to the extremely long running-time with a simulation-based method for large industrial-level designs and the difficulty of constructing test benches that will mimic the activity created by real world use of the circuit. Therefore, most designs today either do not explicitly consider circuit activity during the power analysis and optimization or assume a global toggle rate percentage relative to the frequency of the clock signals for all signals of the circuit, which is far away from reality.
Switching activity analysis is a key missing element for both power estimation and power optimization of the integrated circuits (ICs) as the power consumption becomes one of the bottleneck in the IC design.
The problem definition of a circuit switching activity analysis is as follows: given the state and transition probabilities of all inputs of a circuit, provide state and transition probabilities of all the internal signals and outputs of the circuit. Here, two quantified parameters are used to specify the activities of a signal A: 1) a state probability P(A) (e.g., a probability of signal A at logic 1); and 2) a transition probability T(A) (e.g., a probability of signal A switching from logic 1 to logic 0 or from logic 0 to logic 1).
A straightforward approach of performing a switching activity analysis is simulation traces such as the Monte Carlo Simulation (MCS), which consists of applying randomly generated input patterns at the circuit inputs and counting state and transition probabilities using a simulator. A disadvantage of the MCS is the requirement of a very long test bench to cover a large number of sequences of input patterns which requires a long running time. The number and length of the sequences requires increases rapidly with the number of flip-flops in the circuit since the number of states grows exponentially with the number of flip-flops. Therefore, most designers just simply apply a global switching activity rate on all signals, such as, for example, 25% of the clock frequency.
Another approach is called a vectorless circuit activity analysis or probabilistic-based circuit activity analysis based on signal probability computation. One basic tool used in sequential circuit analysis is the concept of unrolling the circuit which consists of iterating the circuit over-clock cycles. Visually, you can think of multiple copies of a schematic stacked on top of each other with flip-flops replaced by wires connecting the input of the flip-flop on the lower sheet to the output connection of the flip flop on the sheet above. Signal values on the inputs and wires represent the circuit input and state in a first clock cycle and each successive sheet represents the inputs and states in the successive clock cycle. Some have proposed the idea of unrolling the next state logic in order to model a temporal correlation between two consecutive logic states of a finite state machine (FSM), i.e. the internal temporal correlation within the FSM. Further improvement was made by considering a spatial correlation of reconvergent paths. However, none of these methods considers the temporal and spatial correlations of input signals of an unrolled circuit. A simple spatial correlation example is two input signals to a sub-circuit that are never true at the same time, perhaps the output of a counter that counts 0, 1, 2, 0, . . . and never reaches 3. Recently, a close-form formula was proposed to characterize the state probability and switching activity of each single flop that has a feedback loop. However, this method only has the ability to model the temporal-spatial correlation of a state machine with one flop under the assumption of stateless enable signal and correlation-free inputs, which is rarely true.